A DDR-SDRAM is a memory that outputs data at both rising and falling edges of a clock. The DDR-SDRAM outputs a read data signal and a data strobe signal, which is synchronized with the read data signal. The memory interface circuit, which is a request origin of data transfer, refers to the rising edge and the falling edge of the data strobe signal to accurately retrieve the read data signal.
When starting the reading of data, a data strobe line for transmitting the data strobe signal is in a high impedance state during a period in which data is not output from the DDR-SDRAM. After a data read command is input, the data strobe line is set to a low level one cycle prior to when data is output from the memory. Such a low level period is referred to as a preamble period.
A delay circuit is used to divide the data strobe signal into a plurality of data strobe signals having different delay widths. This obtains a plurality of data strobe signals having different input timings. An L period detection circuit distinguishes the phase of the data strobe signals, which are delayed differently by the delay circuit. Further, when the data strobe signal has a low level for a period of one cycle, the L period detection circuit detects the low level period as the preamble period. Japanese Laid-Open Patent Publication No. 2008-293279 describes such a technique for detecting the preamble period of the data strobe signal.
If an internal circuit retrieves the read data signal when the data strobe signal has high impedance, the internal circuit may function erroneously.